Computer memory typically can be divided into two categories: volatile and nonvolatile. Nonvolatile memories retain their data after power is removed. Volatile memory devices retain their data only as long as power is applied.
One type of prior nonvolatile semiconductor memory is the flash electrically erasable programmable read-only memory ("flash EEPROM"). The flash EEPROM can be programmed by a user, and once programmed, the flash EEPROM retains its data until erased. After erasure, the flash EEPROM can be reprogrammed with new data. The same flash EEPROM is typically capable of being cycled (i.e., erased and reprogrammed) thousands of times.
A flash EEPROM is typically comprised of banks of memory cells. Data is stored as digital bits (0's and 1's) in these memory cells with each cell storing one bit of data.
Each individual memory cell within a memory bank typically is indexed by a pair of select lines designated as X-select and Y-select. The X-select word lines specify the row and the Y-select bit lines specify the column of a particular memory cell to be accessed. Decode circuitry is used to interpret input control signals and activate the appropriate select lines to access the desired memory cells.
The verify signals for the decode circuitry are precision voltages controlled over temperature and process skews and are typically generated by a class-A type amplifier, which typically is a weak driver. Consequently, the output signals typically do not have enough current to properly drive the select lines, which typically can have up to five picofarads of capacitance each, depending on their length. Relatively large Complementary Metal Oxide Semiconductor ("CMOS") inverters are typically used to drive the select lines. The CMOS inverters buffer weak decoder output signals from having to drive the large load on the select lines. By driving the appropriate combination of X and Y-select lines, a particular memory cell within a memory cell bank can be accessed.
A typical prior decoder 11 and CMOS driver 12 circuit is shown in FIG. 1. CMOS driver 12 is a CMOS inverter. A control signal is applied as an input on line 100. The decoder 11 receives a logical high addressing input at the gate of transistor 2, and a logical low control signal on line 100, which in turn activates driver 12 to drive word line if the word line is selected 14. Word line 14 has a certain amount of associated capacitance. This capacitance results from the length of word line 14 and the number of flash cells attached to word line 14. This capacitance is depicted in dashed lines as capacitor 15 in FIG. 1. Decoder 11 is a p-channel transistor 2 and is powered by a high voltage line HHVPIX 16. Typical voltages for HHVPIX 16 are 12 volts (V.sub.pp) and 5 volts (V.sub.cc). V.sub.pp is the erase/program power supply voltage for the flash memory, and V.sub.cc is the device power supply.
Driver 12 is comprised of a p-channel transistor 3 and an n-channel transistor 4. Driver 12 is powered by HHVPX 17, which is a high voltage line. The voltage levels on HHVPX 17 vary, depending on the function to be performed. Typical voltage levels and functions for HHVPX 17 are 12 volts (V.sub.pp) for programming, 5 volts (V.sub.cc) for read and standby, 7 volts for program verify, 7 or 5 volts for pre-erase verify, 5 to 10 volts for post-erase-repair, and 2.5 volts for post-erase-repair verify. As an example, to program a memory cell, HHVPX needs to be set to 12 volts (V.sub.pp). A program verify will automatically follow the program step in order to check that the programming was performed satisfactorily. HHVPX 17 needs to be changed to 7 volts in order to perform the program verify.
The p-channel transistor 3 of driver 12 resides in an n-well. In order to keep the p-n junction reverse biased to prevent latch-up, the n-well typically is biased at a voltage level that is greater than or equal to the program voltage This typically is accomplished by tying the n-well to HHVPX 17 as shown by line 18 in FIG. 1.
One problem with the configuration of FIG. 1 is the relatively large capacitance inherent in the diffusion junction between the n-well and the p-substrate for driver 12. Because each word line has a separate driver, the parallel combination of junction capacitances creates a large lumped capacitance. This inherent n-well capacitance is shown in FIG. 1 as capacitor 19.
The n-well capacitance 19 typically detrimentally affects the amount of time required to verify for the different stages. The verify voltages are typically generated by a class-A type amplifier, which provides a precision reference voltage controlled over temperature and process skews. Class-A type amplifiers are typically weak drivers. A relatively long time is typically required to charge and discharge the n-well capacitance 19 whenever the HHVPX voltage level changes (e.g., 12 volts for program versus only 7 volts for program verify). This translates into a longer period of time to perform verifies because the n-well capacitance 19 must be charged and discharged by the weak amplifier.
In the past, memory capacity was relatively small and there were relatively few drivers for driving the memory cells so that the combined effect of the n-well capacitance on the drivers was relatively small. Thus, there was a relatively minor impact on the time required to verify at the different stages.
As memory capacity has increased, however, the cumulative n-well capacitance has correspondingly increased. The n-well capacitance significantly increases the time for verifies for larger flash EEPROMs. Of course, a longer verify time adversely affects the performance of a flash EEPROM.
Another disadvantage of certain prior flash EEPROMs is that HHVPX generators and verify level generators need to be relatively large and powerful in order to supply enough current to drive capacitively loaded word lines. This typically is a result of the n-well capacitance inherent in the drivers.